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Integrated Circuit Systems, Inc.
ICS9250-33
Advance Information
Frequency Generator for Celeron/PIIITM
Recommended Application: Output Features: * 4 Differential CPU Clock Pairs @ 3.3V * 2 - 3V MREF clocks for memory reference seeds, (separate single ended but 180 degrees out of phase) * 4 - 66MHz reference output * 10 - 3V 33MHz PCI clocks * 2 - 48MHz clocks * 2 - 14.318 reference output Features: * Up to 156MHz frequency support * Support power management: Power Down Mode * Supports Spread Spectrum modulation: 0 to -0.5% down spread. * Uses external 14.318MHz crystal * Select logic for Differential Swing Control, Test mode, Tristate, Power down, Spread Spectrum, limited frequency select, selective clock enable. * External resistor for current reference * FS pins for frequency select Key Specifications: * 3V66 Output jitter <300ps * CPU Output Jitter <200ps * MREF Output jitter <250ps
GND MULTSEL0/REF MULTSEL1/REF VDDREF X1 X2 GNDREF PCICLK0 PCICLK1 VDDPCI PCICLK2 PCICLK3 GNDPCI PCICLK4 PCICLK5 VDDPCI PCICLK6 *FS2/PCICLK7 GNDPCI PCICLK8 PCICLK9 VDDPCI SEL100/133 GND48 FS0/48MHz FS1/48MHz VDD48 PD#
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDMREF 3VMREF 3VMREF_B GNDMREF SPREAD# CPUCLKT3 CPUCLKC3 VDDCPU CPUCLKT2 CPUCLKC2 GNDCPU CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GNDCPU I REF VDDA GNDA VDD3V66 3V66-3 3V66-2 GND3V66 GND3V66 3V66-1 3V66-0 VDD3V66
56-Pin 300mil SSOP & TSSOP
* This input has a 120K internal pull down to GND.
Functionality
SEL133/ 100 0 0 0 0 1 1 1 1 FS0 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 Function Active 100MHz 105MHz 200MHz Tristate all outputs Active 133MHz 126MHz 200MHz Test Mode
3VMREF DIVDER
Block Diagram
PLL2
2
ICS9250-33
48MHz
X1 X2
XTAL OSC PLL1 Spread Spectrum
2
REF
CPU DIVDER
4 4
CPUCLKT [0:3] CPUCLKC [0:3]
* FS2 = 1: Margin testing mode
PD# SPREAD# MULTSEL[0:1] SEL100/133 FS[2:0] Control Logic Config. Reg.
3VMREF 3VMREF_B
Power Groups
VDDREF, GNDREF= REF, X1, X2 VDDPCI, GNDPCI = PCICLK VDD48, GND48 = 48MHz, PLL2 VDD3V66, GND3V66=3V66 VDDCPU, GNDCPU = CPUCLK VDDMREF, GNDMREF=3VMREF, 3VMREF_B VDDA=VDD (core supply voltage 3.3V) GNDA=Ground for core supply
9250-33 Rev - 5/14/01 Third party brands and names are the property of their respective owners.
PCI DIVDER
10
PCICLK [0:9]
3V66 DIVDER
4
3V66 [0:3]
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS9250-33
Advance Information
General Description
The ICS9250-33 is a single chip clock solution, for multi processor server or high-end desktop applications. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-33 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER
1, 7, 13, 19, 24, 32, 33, 37, 40, 46, 53 2, 3 4, 10, 16, 22, 27, 29, 36, 38, 43, 49, 56 5 6 8, 9, 11, 12, 14, 15, 17, 20, 21 18 23 25, 26 28 30, 31, 34, 35 39 42, 45, 48, 51 41, 44, 47, 50 52 54 55
PIN NAME
GND REF/MULTSEL [0:1] VDD X1 X2 PCICLK [0:6][8:9] FS21 PCICLK7 SEL100/133 FS [0:1] 48MHz PD# 3V66 [0:3] I REF CPUCLKT [0:3] CPUCLKC [0:3] SPREAD# 3VMREF_B 3VMREF
TYPE
PWR IN PWR X2 Crystal Input
DESCRIPTION
Ground pins for 3.3V supply MULTSEL0 and MULTSEL1 inputs are sensed on power-up and then internally latched prior to the pin being used for output on 3V 14.318MHz clocks. 3.3V power supply 14.318MHz Crystal input
X1 Crystal Output 14.318MHz Crystal output OUT IN OUT IN IN OUT IN OUT OUT OUT OUT IN OUT OUT PCI clock outputs Margin testing frequency select pin PCI clock output CPU Frequency Select. Low=100MHz, High=133MHz Frequency select pins 48MHz clock output Invokes power-down mode. Active Low. 66MHz reference clocks This pin establishes the reference current for the CPUCLK pairs. This pin takes a fixed precision resistor tied to ground in order to establish the required current. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "Complementory" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. Invokes Spread Spectrum functionality on the Differential host clocks, MRef/MRef_b clocks, 66MHz clocks, and 33MHz PCI clocks. Active Low 3V reference to memory clock driver (out of phase with 3Vmref) 3V reference to memory clock driver
Note1: To ensure proper Intel defined frequency is used, an external 10K ohm pull down resistor is recommended
Third party brands and names are the property of their respective owners.
2
ICS9250-33
Advance Information
Truth Table
FS2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL 133/100 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CP U 100MHz 105MHz 200MHz Tristate 133MHz 126.7MHz 200MHz TCLK/2 100.50 105.00 110.00 166.67 133.73 140.00 146.66 156.46 MRef 50MHz 52.5MHz 50MHz Tristate 66MHz 63.3MHz 66.7MHz TCLK/4 50.25 52.50 55.00 83.34 66.86 70.00 73.33 78.23 3V66 66MHz 70MHz 66.7MHz Tristate 66MHz 63.3MHz 66.7MHz TCLK 67.00 70.00 73.34 83.34 66.86 70.00 73.33 78.23 REF 14.318MHz 14.318MHz 14.318MHz Tristate 14.318MHz 14.318MHz 14.318MHz TCLK 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz Spread Percentage 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread*
Note: * 48MHz will be at TCLK/2 frequency if entry 1111 is slected.
Group Offset Limits
Group CPU to 3V66 CPU to PCI 3V66 to PCI 1.5 - 3.5ns 3V66 leads 30pF 1.5V Offset No Requirement Measurement Loads (lumped) Measure Points
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3
ICS9250-33
Advance Information
CPUCLK Buffer Configuration
Conditions Iout Vdd = nominal (3.30V) Configuration All combinations of M0, M1 and Rr shown in table below All combinations of M0, M1 and Rr shown in table below Load Nominal test load for given configuration Nominal test load for given configuration Min -7% I nominal Ma x +7% I nominal
Iout
Vdd = 3.30 5%
-12% I nominal +12% I nominal
CPUCLK Swing Select Functions
MULTSEL0 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.71V @ 60 0.59V @ 50 0.85V /2 60 0.71V @ 50 0.56V @ 60 0.47V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.90V @ 30 0.75V @ 20 0.60 @ 20 0.5V @ 20 1.05V @ 30 0.84V @ 20
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4
ICS9250-33
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5% PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current VIN = 0 V; Inputs with no pull-up resistors IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors IIL2 Operating CL = 0 pF; Select @ 66M IDD3.3OP Supply Current Power Down IDD3.3PD CL = 0 pF; With input address to Vdd or GND Supply Current Input frequency Fi VDD = 3.3 V; Pin Inductance Lpin CIN Logic Inputs Input Capacitance1 Cout Out put pin capacitance X1 & X2 pins CINX 1 Transition Time Ttrans To 1st crossing of target Freq. Settling Time1 Clk Stabilization 1 Delay
1
MIN 2 VSS-0.3 -5 -5 -200
TYP
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 100 600 mA A MHz nH pF pF pF mS mS mS nS nS
27
7 5 6 45 3 3 3 10 10
Ts TSTAB tPZH,tPZH tPLZ,tPZH
From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) 1 1
Guarenteed by design, not 100% tested in production.
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5
ICS9250-33
Advance Information
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1 2
SYMBOL RDSP2B1 RDSN2B1 VOH2B VOL2B IOH2B2 IOL2B2 tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc1 VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA
CONDITIONS
MIN 13.5 13.5 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 45 45 0.4 -27 30 1.6 1.6 55 100 150 V V mA mA ns ns % ps ps
VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 0.4 V, VOL = 2.0 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
Guarenteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - REF TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated)
PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP
MAX UNITS MHz 60 0.4 -23 27 4 4 55 N/A 1000 V V mA mA ns ns % ps ps
dt11 tsk1
1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9250-33
Advance Information
Electrical Characteristics - MREF/MREF_B TA = 0 - 70C; VDD = 3.3 V 5%; CL =10-20 pF (unless otherwise stated)
PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP1 1 VOH1 VOL1 IOH1 IOL1 tr1 1 tf1
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP
MAX UNITS MHz 55 0.4 -33 38 2 2 55 N/A 250 V V mA mA ns ns % ps ps
dt1 1 tsk1
1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated)
PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt1
1 1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP
MAX UNITS MHz 55 0.4 -33 38 2 2 55 250 300 V V mA mA ns ns % ps ps
tsk1 tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9250-33
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PD#
MREF MREF_BAR
CPUCLKT CPUCLKC VCO Crystal
Notes: 1. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
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8
ICS9250-33
Advance Information
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
D (inch) MIN .720 MAX .730
300 mil SSOP Package
Reference Doc.: JEDEC Publication 95, MO-118 10-0034
Ordering Information
ICS9250yF-33-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
9
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS9250-33
Advance Information
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS D mm. MIN MAX 13.90 14.10
-Ce
b SEATING PLANE
N 56
10 -0 0 3 9
D (inch) MIN .547 MAX .555
aaa C
Ref erence D o c.: JEDEC Pub licat io n 9 5, M O-153
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
Ordering Information
ICS9250yG-33-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
10
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

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